The present invention relates generally to semiconductor packaging and manufacturing, and more particularly to a package for a semiconductor die.
Recently, electronic systems have incorporated high-level semiconductor devices, such as integrated circuits, to perform complex processing functions. The integrated circuits include diodes, resistors, capacitors, transistors, and microprocessors. These devices are commonly connected together on the integrated circuit or semiconductor die. The semiconductor die is packaged in a structure which includes terminal connections which may be connected to a printed circuit board or other substrate. The resulting semiconductor die may be connected to multiple integrated circuits to perform multiple functions in the electronic system.
The demand in integrated circuit design has increased toward smaller circuits via miniaturization which can perform more functions. One technique is to increase the functions and decrease the size of the circuit. Another technique is to increase the circuit density of the semiconductor die. To achieve these demands, more input/output connections are formed from the semiconductor die to a surface of the substrate.
Generally, the semiconductor die is initially mounted to a die receiving area. The die protrudes from a surface of the substrate, and is electrically connected to the substrate by the bond wires. Known methods for forming the electrical connections include wirebonding and tape-automated bonding (TAB). In TAB, metal tape leads are attached between bond pads on the semiconductor die and bond pads on the substrate. An encapsulant may be used to cover the bond wires and metal tape leads to prevent contamination. In wirebonding, a plurality of bond wires are attached one at a time from each bond pad on the semiconductor die to a corresponding bond pad on the substrate. After the electrical connections ate formed and the die is encapsulated, a trim and form operation is used to separate the die from the package into individual integrated circuits.
Several types of packaging are known. Typical packages include ball grid array (BGA), flip chip, microBGA, fine pitch BGA, and chip scale packages.
Currently, each of these packages requires special tooling and supplies to form the package. One drawback to the current package designs is that they do not provide adequate structural support for the non-active surface (i.e. the surface of the die which is not connected to the die receiving area) of the semiconductor die during the packaging process. This causes chip failure because the chip tends to crack or fracture. This means that the portion of the tape between adjacent dice tends to crack during the trim and form process. This is because the tape is not adequately supported between adjacent dice on the substrate. Another drawback is that the current substrates do not provide a suitable recessed surface for the TAB applications.
Therefore, a need exists for a semiconductor package that protects the die from cracking or fracturing during a semiconductor packaging process.